OpenRISC

Architecture

The OpenRISC 1000 architecture is a completely open architecture. It defines the architecture of a family of open source, RISC microprocessor cores. The OpenRISC 1000 architecture allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, and scalability. OpenRISC 1000 targets medium and high performance networking and embedded computer environments.

Performance features include a full 32/64-bit architecture; vector, DSP and floating-point instructions; powerful virtual memory support; cache coherency; optional SMP and SMT support, and support for fast context switching. The architecture defines several features for networking and embedded computer environments. Most notable are several instruction extensions, a configurable number of general-purpose registers, configurable cache and TLB sizes, dynamic power management support, and space for user-provided instructions.

Most OpenRISC implementations are designed to be modular and vendor-independent. They can be interfaced with other open-source cores, e.g., available at www.opencores.org. The OpenRISC community encourages third parties to design and market their own implementations of the OpenRISC 1000 architecture and to participate in further development of the architecture.

Basic Features

The OpenRISC instruction set architecture (ISA) is a simple RISC architecture with the following features:

  • Linear 32-bit or 64-bit address space (currently no 64-bit implementations)

  • Uniform-length instructions (32-bit instructions aligned at 32-bit boundaries)

  • ORBIS32/64: Basic instruction set (load/store, arithmetic, logical, ..) operating on 32-bit/64-bit data

  • ORVDX64: Vector/DSP extensions (SIMD) operating on 8-, 16-, 32- and 64-bit data

  • ORFPX32/64: Floating point extensions operating on 32-bit/64-bit

  • Two simple addressing modes: Register indirect with displacement and PC relative

Architecture Revisions

The OpenRISC architecture specification is community driven and revisions can be proposed by anyone.

The revision process is:

  • Create a new proposal by copying the proposal template in the in the openrisc.io project and making a pull request.
  • Send a mail to the linux-openrisc@vger.kernel.org mailing list for discussion.
  • Once a critical mass of proposals are made we will discuss the final cut of changes.
  • Once the final proposals are decided a volunteer will update the odt and pdf docs and post back to this Specification page with a new revision.
  • After the proposal is added to the specification and the revision page is create mark all proposal drafts as accepted.

Published Versions

This is a list of historical revisions that have been reviewed, signed-off and published.

Version 1.4

2022-02-20

  • Download pdf
  • Changes
    • Change FPCSR SPR permissions to allow for reading and writing from user space.
    • Clarify that FPU underflow detection is done by detecting tininess before rounding.
  • Authors Stafford Horne shorne@gmail.com

Version 1.3

2019-06-04

  • Download pdf
  • Changes
    • ORFPX64A32 double-precision floating point operations on 32-bit hardware using register pairs (P14)
    • Define CPUCFGR[15] for ORFPX64A32 presence flag
    • New instructions lf.stod.d lf.dtos.d for converting between single and double precision floats (P7)
    • New instruction l.adrp for constructing addresses (P9)
    • New instructions lf.sfun* to support unordered compares (P11)
    • New instruction l.lf to load floats with NaN boxing on 64-bit hardware
    • Removed instructions lf.rem.d and lf.rem.s used to calculate floating point remainder
    • Various cleanups and clarifications on internal rounding, truncation and others
      • Clarification on internal rounding for lf.madd.* instructions (P6)
      • Update l.div* to mention fraction is truncated
      • Update lf.ftoi.* to mention fraction is truncated (P13)
      • Add single-precision floating point NaN boxing on 64-bit hardware
      • Updated machine instruction table (Section 18), removed unused page column, added class and opcode for quick reference
      • Document lf.sf* floating point exceptions
      • Document that floating point exceptions do write back results to registers
      • Define addresses for FPMADD* and VMAC* sprs
  • Authors Stafford Horne shorne@gmail.com, Andrey Bacherov bandvig@mail.ru

Version 1.2

2017-10-21

  • Download pdf
  • Changes
    • Core Identifier and Number of Cores (P1)
    • Reserve register r10 for thread local storage (P15)
    • Clarification on Atomic Boundaries (P16)
    • Various typos fixes and cleanups
    • Multicore support and ompic
  • Author Stafford Horne shorne@gmail.com

Version 1.1

2014-05-12

  • Download pdf
  • Changes
    • Adds support for l.lwa and l.swa atomic operations

Version 1.0

2012-12-14

This was the first update to OR1K architecture for many years. It addresses architectural and documentation issues in the manual.

  • Download pdf
  • Changes
    • jump/branch delay slot is now optional
    • improved version tracking
    • relocatable exception vector space
    • correction of arithmetic overflow and carry detection
    • improvements to MAC and integer multiply behaviour
    • various clarifications regarding hardware and software behaviour

Old Specification

2006-04-01

This is the original spec kept here for archive purposes.

Proposals

This is a list of currently pending proposals.

Instruction Classes (P5)

2012-04-21 - Julius

At present, there are class I and II instructions. Class I must always be implemented. Class II may be optionally implemented.

l.lw assembly mnemonic (P4)

2012-05-16 - Julius

Add the l.lw assembly mnemonic, which encodes as a l.lwz instruction.

SPR access updates (P3)

2015-03-03 - Wallento

There has been a discussion about different SPRs and the possibility to access them from user space.

Optional user-mode support (P2)

2015-03-03 - Wallento

As some processors designed for embedded applications won’t necessarily run software with a user/supervisor-mode split of operation, it’s not necessary for them to implement user-mode features (eg. protect from unprivileged access to SPRs and the like.) Obviously this lack of support for user mode should be indicated via a bit in the CPUCFGR. So I propose a bit is added so that implementations without user-mode support can be detected by software which requires user-mode.

ORBIS64/ORFPX64 Additions - l.lda, l.sda (P8)

2015-03-06 - Rth

We need 64-bit atomic memory ops, akin to the l.lwa and l.swa instructions for ORBIS32. Use major opcodes 0x3a (l.lda) and 0x3b (l.sda).

ORBIS64/ORFPX64 Additions - l.movl, l.addl (P10)

2015-03-06 - Rth

We need an efficient method of forming 64-bit constants. Currently it takes 5 insns and two registers, or 6 insns and one register to form a full 64-bit constant. Propose extending opcode 0x06 (l.movhi/l.macrc) to be able to form a 64-bit constant (or add a 64-bit displacement!) in only 4 insns:

ORBIS64/ORFPX64 Additions - ACC instructions (P12)

2015-03-06 - Rth

At present, the SPRs are defined to be 32-bits wide, which restricts the width of the MACHI:MACLO accumulator register. This is emphasized by the definition of the l.macrc instruction. Further, user-space access to MACHI and MACLO SPRs may be disabled by the kernel via SR[SUMRA]. Better to introduce another method of performing double-word arithmetic and accumulation that does not depend on SPRs at all.