OpenRISC

Version 1.2

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  • Changes
    • Core Identifier and Number of Cores (P1)
    • Reserve register r10 for thread local storage (P15)
    • Clarification on Atomic Boundaries (P16)
    • Various typos fixes and cleanups
    • Multicore support and ompic
  • Author Stafford Horne shorne@gmail.com

Details of Additions/Changes

Core Identifier and Number of Cores (P1)

2015-03-03 - Wallento

To enable multicore systems, a Special Purpose Register ‘Core ID’ is needed. Although it is principally not necessary, but allows for a self-contained solution, I furthermore propose a ‘Number of Cores’ register, which contains the number of cores in a SMP cluster.

Designation of r10 for TLS (P15)

2017-08-18 - Stafford Horne

In the Linux kernel and GCC r10 is already being used for TLS, so add it to the spec.

Clarification on Atomic Boundaries (P16)

2017-08-18 - Stafford Horne

Section 7.3 Atomicity explains that a upon load a reservation is made at the address of the load memory location and that subsequent stores to the same memory location will cancel the reservation. It is not clear whether stores of byte or half-word size overlapping the memory location cause reservation cancellation.