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  • Changes
    • ORFPX64A32 double-precision floating point operations on 32-bit hardware using register pairs (P14)
    • Define CPUCFGR[15] for ORFPX64A32 presence flag
    • New instructions lf.stod.d lf.dtos.d for converting between single and double precision floats (P7)
    • New instruction l.adrp for constructing addresses (P9)
    • New instructions lf.sfun* to support unordered compares (P11)
    • New instruction l.lf to load floats with NaN boxing on 64-bit hardware
    • Removed instructions lf.rem.d and lf.rem.s used to calculate floating point remainder
    • Various cleanups and clarifications on internal rounding, truncation and others
      • Clarification on internal rounding for lf.madd.* instructions (P6)
      • Update l.div* to mention fraction is truncated
      • Update lf.ftoi.* to mention fraction is truncated (P13)
      • Add single-precision floating point NaN boxing on 64-bit hardware
      • Updated machine instruction table (Section 18), removed unused page column, added class and opcode for quick reference
      • Document lf.sf* floating point exceptions
      • Document that floating point exceptions do write back results to registers
      • Define addresses for FPMADD* and VMAC* sprs
  • Authors Stafford Horne shorne@gmail.com, Andrey Bacherov bandvig@mail.ru

Details of Additions/Changes

ORBIS64/ORFPX64 Additions - l.adrp (P9)

2015-03-06 - Rth

We need an efficient method of forming 64-bit addresses. The fact that this will improve -fpic code generation in 32-bit mode too is an added bonus.

ORBIS64/ORFPX64 Additions - l.stod, l.dtos (P11)

2015-03-06 - Rth

The ORFPX64 extension is missing instructions to convert between single and double precision.

ORBIS64/ORFPX64 Corrections (P13)

2015-03-06 - Rth

Multiple corrections to the 64-bit istructions specfication.

ORFPX32/ORFPX64 - lf.madd (P6)

2015-03-06 - Rth

The description of these instructions needs to make it clear that the result is computed without intermediate rounding. See the ISO C 99 functions fma and fmaf.

ORFPX32/ORFPX64 - lf.sf* (P7)

2015-03-06 - Rth

The current definitions of comparisons do not allow easily testing the “unordered” property, which is important in the presence of NaNs. There are four conditions for which we might want to test, which when combined produce all of the possible results. Referencing the ISO C 99 functions:

ORFPX64A32 (P14)

2015-03-12 - BAndViG

Adaptation double precision floating point ISA for 32-bit OR1K architecture. The idea is analogue to other 32-bit architectures. Namely use paired GPRs to perform operations with double precision floating point data.