OpenRISC Project Overview
Welcome to the project overview of the OpenRISC project. The major goal of the project it to create a free and open processor for embedded systems. This includes:
a free and open RISC instruction set architecture with DSP features
a set of free, open source implementations of the architecture
a complete set of free, open source software development tools, libraries, operating systems and applications
a variety of system-on-chip and system simulators
The project is driven by a very active community and has a long history. This unfortunately lead to scattered and partly outdated information. The goal of this page is to provide an overview over active parts of the project and the current development to ease the entry for newcomers or people seeking basic information. The information is collected from the following sites where you can find more information (which can be partly outdated):
The very quick start: jor1k
If that’s not enough, feel free to compile your own code and run it in the simulator. There also is a demo where you can edit, compile and run inside the browser, so that you don’t even need a cross-compiler toolchain!
There are two mainline processor core implementations:
OR1200 is the original first implementation of the processor in Verilog. It implements the basic features and is still widely used, although not actively developed.
mor1kx is a novel implementation which is more sophisticated and has different variants with respect to the number of pipeline stages, tightly coupled memory or the presence of a delay slot. It has also been recently extended to support atomic operations and multicore features.
If you want to start with simulating the processor core to just try it out, you have the following options:
or1ksim is an instruction accurate simulator with a lot of features including flexible configuration and gdb debugging.
qemu has a patch to support the OpenRISC processor
While a processor core is still the heart of every system, the peripherals, memory etc. are of course equally important. There are a number of system-on-chip available that you can use to perform RTL simulations, SystemC simulations or perform an FPGA synthesis of an OpenRISC-powered entire system:
fusesoc is a new SoC generator that not only supports OpenRISC. It also manages the available peripheral cores and allows you to easily configure and generate your system-on-chip.
minsoc is a minimal OpenRISC-based system-on-chip, that is easy to configure and implement, but still uses the OR1200 processor implementation.
OpTiMSoC is a flexible multicore system-on-chip that is based on a network-on-chip and connects a configurable number of OpenRISC (mor1kx) processors to arbitrarily large platforms.
MiSoC is a SoC generator using the Python based Migen which can use the mor1k processor. Both high performance and optimized for small FPGA footprint, it supports a large number of development boards out the box.
If you want to run an operating system on your OpenRISC you have a few options:
Linux has been ported and is now upstream in the standard Linux repositories (upstream is the term that denotes that you submitted your changes to an open source project and they have been accepted and are now part of this software)
RTEMS has been ported during a Google Summer of Code project and is also upstream.
A few toolchains are generally supported. A C library is an essential part of your toolchain as it provides you the basic features. The following toolchains with different C libraries are available:
newlib is a small library mainly used for baremetal usage. We also maintain a port of it for the baremetal toolchain
musl is a new C library with a strong emphasis on being light-weight and correctness. There also is a full toolchain
uClibc-ng a reboot of the uClibc project, is a similar small library and primarily used for Linux applications.
or1k-linux-uclibc-gccis the standard toolchain for Linux at the moment.
Cross compiling applications to your OpenRISC embedded target and packaging them up into a root filesystem image could be tedious. There are a few options to smooth the process:
Buildroot has support for building applications using the uClibc-ng toolchain.
OpenADK from the maintainers of uClibc-ng has support for building using both uClibc-ng and musl toolchains.
28 May 2021 »
Google Summer of Code 2021
(Stafford Horne) The Google Summer of Code is a yearly event which teams open source projects with college students. Students learn about technology and the open source community and projects benefit from new contributions. As in previous years this year OpenRISC is participating as part of the FOSSi foundation project. This year..... more
04 Jun 2019 »
Announcing Architecture Version 1.3
(Stafford Horne) It has been been a few years since the release of OpenRISC version 1.2. But, it’s been a busy few years of getting GDB and GCC ports upstream. Now with the GCC port upstream we are able to make progress and this new architecture revision does just that bringing in..... more
27 May 2019 »
Google Summer of Code 2019
(Stafford Horne) The Google Summer of Code is a yearly event which teams open source projects with college students. Students learn about technology and the open source community and projects benefit from new contributions. As in previous years this year OpenRISC is participating as part of the FOSSi foundation project. We have..... more
09 Nov 2018 »
GCC Upstream for 9.0.0
(Stafford Horne) We are proud to announce that the OpenRISC port for gcc has been committed to upstream. Mainline OpenRISC support will be available in the upcoming 9.0.0 release of GCC. Note, this has been a clean room rewrite of the OpenRISC gcc port. The old port can still be found in..... more
16 Mar 2018 »
GDB Upstreaming and Binaries: 7.2.0
(Stafford Horne) We are proud to announce that the OpenRISC port for gdb has been merged upstream. This was done back in December 2017 so its a bit late notice, but here it is. With that we have released an updated version of the toolchain with x86_64 binaries for easy consumption. The..... more