OpenRISC Project Overview
Welcome to the project overview of the OpenRISC project. The major goal of the project it to create a free and open processor for embedded system. This includes:
a free and open RISC instruction set architecture with DSP features
a set of free, open source implementations of the architecture
a complete set of free, open source software development tools, libraries, operating systems and applications
a variety of system-on-chip and system simulators
The project is driven by a very active community and has a long history. This unfortunately lead to scattered and partly outdated information. The goal of this page is to provide an overview over active parts of the project and the current development to ease the enty for newcomers or people seeking basic information. The information is collected from the following sites where you can find more information (which can be partly outdated):
The very quick start: jor1k
If that’s not enough, feel free to compile your own code and run it in the simulator. There also is a demo where you can edit, compile and run inside the browser, so that you don’t even need a cross-compiler toolchain!
There are two mainline processor core implementations:
OR1200 is the original first implementation of the processor in Verilog. It implements the basic features and is still widely used, although not actively developed.
mor1kx is a novel implementation which is more sophisticated and has different variants with respect to the number of pipeline stages, tightly coupled memory or the presence of a delay slot. It has also been recently extended to support atomic operations and multicore features.
If you want to start with simulating the processor core to just try it out, you have the following options:
or1ksim is an instruction accurate simulator with a lot of features including flexbile configuration and gdb debugging.
qemu has a patch to support the OpenRISC processor
While a processor core is still the heart of every system, the peripherals, memory etc. are of course equally important. There are a number of system-on-chip available that you can use to perform RTL simulations, SystemC simulations or perform an FPGA synthesis of an OpenRISC-powered entire system:
fusesoc is a new SoC generator that not only supports OpenRISC. It also manages the available peripheral cores and allows you to easily configure and generate your system-on-chip.
minsoc is a minimal OpenRISC-based system-on-chip, that is easy to configure and implement, but still uses the OR1200 processor implementation.
OpTiMSoC is a flexible multicore system-on-chip that is based on a network-on-chip and connects a configurable number of OpenRISC (mor1kx) processors to arbitrarily large platforms.
MiSoC is a SoC generator using the Python based Migen which can use the mor1k processor. Both high performance and optimized for small FPGA footprint, it supports a large number of development boards out the box.
If you want to run an operating system on your OpenRISC you have a few options:
Linux has been ported and is now upstream in the standard Linux repositories (upstream is the term that denotes that you submitted your changes to an open source project and they have been accepted and are now part of this software)
RTEMS has been ported during a Google Summer of Code project and is also upstream.
A few toolchains are generally supported. A C library is an essential part of your toolchain as it provides you the basic features. The following toolchains with different C libraries are available:
newlib is a small library mainly used for baremetal usage. We also maintain a port of it for the baremetal toolchain
musl is a new C library with a strong emphasis on being light-weight and correctness. There also is a full toolchain
uClibc is a similar small library and primarily used for Linux applications.
or1k-linux-uclibc-gccis the standard toolchain for Linux at the moment.
20 Mar 2016 »
Newlib Release: 2.3.0-1
(Stefan Wallentowitz) We have released an updated version of the baremetal toolchain with the newlib C library. The release is based on the newlib 2.3.0 release and contains a few backport patches for or1k bugfixes since then. We have released full toolchains with the following versions: Binutils 2.26 Newlib 2.3.0 plus or1k..... more
15 Mar 2016 »
Mailing list has moved
(Stefan Wallentowitz) As the previous mailing list at opencores.org is not fully maintained anymore, we have created a new one under the umbrella of the community project librecores.org. By having this mailing list under control of the active maintainers of the OpenRISC project we hope to give it much more stability. Please..... more
01 Feb 2015 »
Newlib upstream new
(Stefan Wallentowitz) The newlib port for baremetal applications is now entirely upstream. That means, you can now build libgloss and the newlib libc from the official repositories. Unfortunately we missed the deadline for the 2.20 release by just a few files, but the newlib community recently changed to sub-releases, so that the..... more
15 Oct 2014 »
ORCONF 2014 - a great success
(Stefan Wallentowitz) The OpenRISC Conference 2014 was held in Munich on the weekend of October 11 and 12, 2014. 36 participants visited the conference which covered some very interesting topics again. It was a great thing that the RISC-V guys made it over and we had a great insight to their ISA..... more
14 Oct 2014 »
New OpenRISC landing page
(Stefan Wallentowitz) For newcomers, but also for active members in the community, it was quite hard lately to find information around the internet. The opencores website and wiki look less and less appealing and need some serious work to provide the updated information. Other information, such as the Linux port or new..... more