FuseSoC

Summary

  • License: GPL v3
  • Language: Python (imports both Verilog and VHDL cores)
  • Status: Under active development

Description

FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code.

Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

The package manager part can be seen as an apt, portage, yum, dnf, pacman for FPGA (Field-Programmable Gate Array)/ASIC (Application-Specific Integrated Circuit) IP cores. A simple ini file describes mainly which files the IP core contains, which other IP cores it depends on and where FuseSoC shall fetch the code.

A collection of cores together with a top-level is called a system, and systems can be simulated or passed through the FPGA vendor tools to build a loadable FPGA image.

Currently FuseSoc supports simulations with ModelSim, Icarus Verilog, Verilator, Isim and Xsim. It also supports building FPGA images with Xilinx ISE and Altera Quartus.

ORPSoC

minSoC

OpTiMSoC

MiSoC

Summary

Description

Built on Migen, MiSoC provides a high performance, flexible and lightweight solution to build system-on-chips for various applications.

  • CPU options:
    • LatticeMico32, modified to include an optional MMU (experimental).
    • mor1kx, a better OpenRISC implementation.
  • High performance memory controller capable of issuing several SDRAM commands per FPGA cycle.
  • Supports SDR, DDR, LPDDR and DDR2.
  • Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI flash controller, Ethernet MAC, and more.
  • High performance: on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
  • Low resource usage: basic implementation fits easily in Spartan-6 LX9.
  • Portable and easy to customize thanks to Python- and Migen-based architecture.
  • Design new peripherals using Migen and benefit from automatic CSR maps and logic, simplified DMAs, etc.
  • Possibility to encapsulate legacy Verilog/VHDL code.