We're pleased to announce that ORCONF 2016 will be held between October 7 to October 9 at the University of Bologna, in Bologna, Italy.
ORCONF is an open source digital design and embedded systems conference, covering areas of electronics from the transistor level up to Linux user space and beyond. Expect presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name a few.
Begun as the annual OpenRISC developers and users conference, it has become a broad open source digital design-oriented event and is supported by FOSSi - the Free and Open Source Silicon Foundation.
The conference is free to attend, and we invite anyone with an interest in the field to participate by presenting or just joining us for the event.
Please register to attend via this form, and we will be in touch with further details of the event.
If you would like to present this year, please fill out this form and the organisers will get back to you within a few weeks.
We will be open to presentation submissions up until about a week before the event. The later you submit the less likely it is you'll get your requested time slot and duration. It's also possible we'll fill up, in which case we'll say so here, but we'll try and accommodate everyone who makes an appropriate submission.
The conference will take place at the University of Bologna in Bologna, Italy.
Bologna is easily accessible via air, rail and road. Wikivoyage has a reasonable guide on transport options.
It is a city of a few-hundred thousand people, and there should be plenty of accommodation options available through the usual booking sites.
Two hotels which have been booked by conference organisers and attendees are Hotel Renzo and Hotel Centrale.
Conference start and end
The conference will begin at 1PM on Friday October 7th and conclude at 3PM on Sunday October 9th.
We will aim to provide a running order at least a week before the event.
As is tradition we will endeavour arrange a dinner on Saturday evening which can accommodate all conference attendees and any family or friends who might be in town with them.
Everyone is invited to attend, but must cover their own cost. We're still looking for a suitable venue in Bologna (get in touch if you have a suggestion!) and will announce the arrangements closer to the event.
Innovation in hardware is slowing due to rising costs of chip design and diminishing beneﬁts from Moore’s law and Dennard scaling. Software innovation, on the other hand, is ﬂourishing, helped in good measure by a thriving open-source ecosystem. We believe that open source can similarly help hardware innovation, but has not yet due to several reasons. We identify these reasons and how the industry, academia, and the hardware community at large can come together to address them. IEEE Computer paper.
Presenter: Gagan Gupta
Gagan Gupta leads research efforts related to chips for DNA storage and post-Moore’s Law microprocessors at Microsoft Research. Gupta has held leadership positions across engineering and research in the industry for over two decades. He has designed computer chips that have shipped in millions of path-breaking systems such as Silicon Graphics workstations, Sony Playstations and Huawei routers. He has authored multiple award-winning publications and his work has been covered by New York Times, EE Times, Microprocessor Report, Engineering & Technology, Business Wire, Electronic Design, and New Electronics.
BOOM is an open source superscalar out-of-order RISC-V core that is roughly equivalent in performance and area to a Cortex A9 or A15 processor. BOOM supports the full RV64G RISC-V ISA (including the Privileged and External Debug specifications), provides good single-thread performance competitive with contemporary processors, is written in a free and open hardware construction language (Chisel), targets both ASIC and FPGA flows, and is accompanied by an open source design specification.
In this talk we will discuss some of the latest updates to BOOM and the larger Rocket-chip SoC ecosystem that BOOM integrates with. We will also discuss the new Chisel3 hardware construction language and its new FIRRTL-based (a Flexible IR for RTL) flow, which helps open up the world of writing compiler passes to hardware designers for fun and profit.
Presenter: Chris Celio
Chris Celio is a PhD candidate at UC Berkeley advised by Krste Asanovic and David Patterson. He received his B.S. and M.Eng. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. For his PhD thesis, he has been designing and implementing the open source processor BOOM, with the goal to provide a high-quality and high-performance core for the community to use for research, education, and industry.
Yosys is a free and open source Verilog synthesis tool and more. It gained prominence last year because of its role as synthesis tool in the Project IceStorm FOSS Verilog-to-bitstream flow for iCE40 FPGAs. This presentation however dives into the Yosys-SMTBMC formal verification flow that can be used for verifying formal properties using bounded model checks and/or temporal induction.
The presentation covers practical examples of how to set up and use the flow, but also touches on in-depth topics such as the scheme used by Yosys-SMTBMC to encode a temporal circuit problem using the SMT-LIB v2.5 language (utilizing uninterpreted functions and user-declared sorts).
Clifford Wolf is the author of Yosys, Project IceStorm, and a few other FOSS projects. His interests and hobbies are FOSS EDA, formal methods, data science and machine learning, GPGPUs, the game of Go, and riding an electric unicycle.
Now that FPGAs have become powerful and ubiquitous enough, there exist many soft core CPUs that can be placed within FPGAs to accomplish sequential tasks. Among these are the proprietary CPU's Microblaze and Nios, as well as the open CPUs of OpenRISC and RISC-V. These CPUs, however, tend to be built with the generic purpose of turning an FPGA into a high quality CPU, rather than complementing the FPGA's strength by augmenting some specialized FPGA algorithm with some amount of sequential logic. This focus can be seen in both the area these CPUs take up, as well as the complexity of their interface to the rest of the FPGA's logic and memory.
In contrast, the ZipCPU has been designed from the ground up with a focus on simplified logic and on-chip interaction. It does this by using a stripped down instruction set, as well as a stripped down interrupt and wishbone bus model. This allows the ZipCPU to fit within the small spaces left over within larger designs, as exemplified by the fact that it can easily fit within a Spartan-LX4, using only 1215 LUTs.
Dr. Gisselquist is the lead engineer and owner of Gisselquist Technology, LLC, a services based company focused on providing superior Computer Engineering and Signal Processing services to our customers. Dr. Gisselquist has an M.S. in Computer Engineering and an Ph.D. in Electrical Engineering from the U.S. Air Force Institute of Technology. His current work has been focused on the ZipCPU, and the environment, toolsuite, and peripherals necessary to support both it and any customer applications.
Vlang is a hardware verification DSL created on top of the D programming language. It supports reasonably complex constrained randomization. Vlang provides a multicore enabled port of the UVM 1.2 library and compiles natively to C/C++ compatible shared objects/executables.
Vlang is a self-funded opensource verification language, made available under generous Boost/Apache license terms. Over the past four years, it has grown into more than a hundred thousand lines of code (including the UVM 1.2 port). Puneet Goel is the main developer of the Vlang project. Earlier published three papers on Vlang:1, 2, 3. A DAC 2016 University booth proposal can be seen here
Presenter: Puneet Goel
ESL and chip-verification expert with 20 years of VLSI industry experience. Involved in spec-to- silicon cycle on 7 chip tapeouts in various roles. Actively contributed to SystemC P1666-2011 standard as technical review committee member.
OpenPiton is an open source manycore research platform and the world's first open source, general-purpose, multithreaded, manycore processor. The platform is open source from the applications running on Debian Linux at the top, all the way down to the RTL, ASIC/FPGA synthesis scripts, and ASIC backend scripts. ASPLOS '16 Conference Paper.
This talk will discuss OpenPiton's capabilities, some of the systems we have built on ASIC and FPGA using the platform, and the future direction of making it a baseline platform for manycore research in architecture, compilers, systems, networks, EDA, programming languages, and beyond.
Jonathan Balkind is a PhD Candidate at Princeton University, advised by Professor David Wentlaff. Besides his time spent working on the OpenPiton platform, his research focuses on developing computer architectures inspired by techniques from the world of functional programming.
A complete implementation and measurements of a 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves.
Presenter: Elkim Roa
A professor at Universidad Industrial de Santander, received a B.S. in Electrical Engineering from Universidad Industrial de Santander, Colombia, M.Sc. in Electrical Engineering from University of Sao Paulo, Brazil, and a Ph.D. from Purdue University. I have worked for Rambus designing high-speed SERDES circuits. Currently working on an out-of-order 64-bit SoC.
Jenkins is one of the leading open-source automation servers. It’s a framework, which can be adjusted to a particular area with help of its flexibility and plugin system. Many open-source hardware and embedded projects build their Continuous Integration and Delivery flows with Jenkins, because there is not so many tools in the area.
In the talk I would like to cover common use-cases of Jenkins in hardware projects like integration with EDA tools and hardware peripherals like FPGAs and reporting of build, test and coverage reports. After that I’ll share one of two case studies about integration of Jenkins into hardware projects. If I achieve something presentable with the ongoing project by the conference, one of the case studies will be about FuseSoC integration with Jenkins.
Presenter: Oleg Nenashev
Oleg is a member of the core team in the Jenkins open-source project. He has 10 years of experience in hardware and embedded areas (R&D and automation) at companies like Intel, Sitronics and Synopsys. He also has a PhD degree in Hardware Engineering from St. Petersburg Polytechnic University. His R&D activities were related to embedded processor core and IP design; research areas – automated hardware reengineering, branch prediction and SoC architectures. Oleg’s research project at the university was based on OpenRISC. On the automation front he was leading large-scale automation infrastructure projects, which were hosting dozens of HW and SW products. In open-source In the Jenkins project Oleg participates in the core and plugin development, organizes community events like Google Summer of Code and Jenkins meetups.
LimeSDR is an affordable, wideband, 2x2 MIMO software-defined radio (SDR) peripheral that features a Lime Microsystems field-programmable RF (FPRF) transceiver, Altera Cyclone IV FPGA with ~40K logic elements, plus a Cypress USB 3.0 controller. It is open source hardware, with the PCB design database, FPGA RTL and Cypress FX3 firmware all provided under liberal licensing, together with an accompanying host driver.
The LimeSDR board is also very close in architecture to another Myriad-RF design, the STREAM FPGA development platform, for which an OpenRISC SoC design exists with I/Q streaming interface support. The current LimeSDR FPGA platform provides support for features such as digital up/down conversion and sample timestamps (required for e.g. timing critical cellular systems). However, there is also the potential for implementing many other capabilities in the FPGA, in order to offload the host processor, enable support for new applications and perhaps even enable standalone use.
It is proposed to host a tabletop demonstration of the LimeSDR during breaks at ORCONF.
Presenter: Andrew Back
LimeSDR is a project developed via the Myriad-RF initiative, for which I am the community manager.
ORCONF and FOSSi are looking for sponsors help to cover the costs of this year's event.
Please get in touch if you'd like to support us this year.